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USB97C242 USB 2.0 Flash Drive Controller
Datasheet
Product Features
2.5 Volt, Low Power Core Operation 3.3 Volt I/O with 5V input tolerance Complete USB Specification 2.0 Compatibility
- - Includes USB 2.0 Transceiver A Bi-directional Control and a Bi-directional Bulk Endpoint are provided.
Double Buffered Bulk Endpoint
- - - Bi-directional 512 Byte Buffer for Bulk Endpoint 64 Byte RX Control Endpoint Buffer 64 Byte TX Control Endpoint Buffer
Internal or External Program Memory Interface
-
Complete System Solution for interfacing SmartMedia (SM), and NAND flash devices to USB 2.0 bus
- - Supports USB Bulk Only Mass Storage Compliant Bootable BIOS Support for the following devices: - SM: 2M -15MB/sec - NAND Flash: 2M - 15MB/sec Built-in hardware 1-bit ECC support. Provides low speed control functions 30 Mhz execution speed at 4 cycles per instruction average 12K Bytes of internal SRAM for general purpose scratchpad 768 Bytes of internal SRAM for general purpose scratchpad or program execution with external flash
48K Byte Internal Code Space or optional 64K Byte External Code Space using Flash, SRAM, or EPROM memory.
On Board 12Mhz Crystal Driver Circuit Internal PLL for 480Mhz USB2.0 Sampling, 30Mhz MCU clock Supports firmware upgrade via USB bus if sectorerasable Flash program memory is used 7 GPIOs for special function use: LED indicators, button inputs, power control to memory devices, etc.
- Inputs capable of generating interrupts with either edge sensitivity
- - - - -
8051 8 bit microprocessor
100 Pin TQFP (12x12x1.4 body) package; green, lead-free package also available
ORDERING INFORMATION
Order Number(s): USB97C242-MN-xx for 100 pin TQFP package USB97C242-MV-04 for 100 pin TQFP package (green, lead-free)
SMSC USB97C242
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DATASHEET
USB 2.0 Flash Drive Controller Datasheet
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright (c) 2006 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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TABLE OF CONTENTS
CHAPTER 1 CHAPTER 2 2.1 GENERAL DESCRIPTION ...................................................................................................................4 ACRONYMS & DEFINITION ................................................................................................................6
Acronyms.........................................................................................................................................................6 PIN TABLES.........................................................................................................................................7
CHAPTER 3 3.1
100 Pin List ......................................................................................................................................................7 PIN CONFIGURATION .........................................................................................................................9 BLOCK DIAGRAM .............................................................................................................................10 PIN DESCRIPTIONS ..........................................................................................................................11
CHAPTER 4 CHAPTER 5 CHAPTER 6 6.1
Buffer Type Descriptions................................................................................................................................14 DC PARAMETERS .............................................................................................................................15
CHAPTER 7
7.1 Maximum Guaranteed Ratings ......................................................................................................................15 7.1.1 Capacitance TA = 25C; FC = 1MHz; VDD, VDDP = 2.5V .....................................................................17 CHAPTER 8 CHAPTER 9 CHAPTER 10 CHAPTER 11 CHAPTER 12 AC SPECIFICATIONS ........................................................................................................................18 PACKAGE OUTLINE..........................................................................................................................19 REFERENCE ..................................................................................................................................20 GPIO USAGE TABLE .....................................................................................................................21 TYPICAL APPLICATION ................................................................................................................22
LIST OF FIGURES
Figure 4.1 - 100 Pin TQFP ............................................................................................................................................9 Figure 9.1 - 100 Pin TQFP Package Outline, 12x12x1.4 Body (Rev A).......................................................................19
LIST OF TABLES
Table 3.1 - USB97C242 100 Pin Package ....................................................................................................................7 Table 3.2 - 100 Pin TQFP .............................................................................................................................................7 Table 6.1 - USB97C242 Pin Descriptions....................................................................................................................11 Table 6.2 - USB97C242 Buffer Type Descriptions .......................................................................................................14 Table 7.1 - DC Electrical Characteristics .......................................................................................................................15 Table 9.1 - 100 Pin TQFP Package Parameters (Rev A) ............................................................................................19 Table 11.1 - GPIO Usage.............................................................................................................................................21
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USB 2.0 Flash Drive Controller Datasheet
Chapter 1
General Description
The USB97C242 is a USB2.0 Bulk Only Mass Storage Class Peripheral Controller intended for supporting SmartMedia (SM), and NAND flash memory devices. It provides a single chip USB reader solution for the SM and NAND flash devices in the market*. The device consists of a USB 2.0 PHY and SIE, buffers, Fast 8051 microprocessor with expanded scratchpad, and program SRAM, 48KB program ROM and SM controller. Provisions for optional external Flash Memory up to 64K bytes for program storage is provided. 12K bytes of scratchpad SRAM and 768Bytes of scratchpad SRAM are also provided. Seven GPIO pins are for the 100-pin device. Provisions are made to allow dynamic attach and re-attach to the USB bus to allow hot swap of flash media to be implemented. SMSC provides the following object code software and licenses free of charge with purchase of the USB97C242**: Windows 98 Mass Storage Class driver. Windows application for programming VID/PID/OEM strings, and unique serial number into serial EEPROM (SM reader) or NAND Flash via USB. Production test and format utilities Password protection API and example applet. Firmware with field upgrade capability via USB (requires external specific model 128KB Flash for firmware storage). The Internal program code provides the following features: Support for 1 to 8, 128Mb through 2Gb, 512byte and 2048 byte page size, 8bit parallel NAND flash memories, including multiple memory aggregates in multi-chip-modules (MCM) up to 8, 2Gb devices (ie 16Gb), as long as individual memory device Chip Enables are pinned out in the MCM. Autodetection of NAND Flash memory type and capacity Supports write protect switch Wear leveling Internal VID/PID/Serial Number/OEM String storage in NAND flash itself, eliminating need for external serial EEPROM High performance transfers (interleaving, copy block caching, etc.) Drive password protection SMSC may make complete internal specifications available for those customers requiring programming information, subject to SMSC's applicable Proprietary Information Agreement (nondisclosure agreement). Contact your SMSC sales representative for more information.**
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USB 2.0 Flash Drive Controller Datasheet
Note: * In order to develop, make, use, or sell readers and/or other products using or incorporating any of the SMSC devices made the subject of this document or to use related SMSC software programs, technical information and licenses under patent and other intellectual property rights from or through various persons or entities, including without limitation media standard companies, forums, and associations, and other patent holders may be required. These media standard companies, forums, and associations include without limitation the following: Sony Corporation (Memory Stick), SD3 LLC (Secure Digital/MultiMediaCard), the SSFDC Forum (SmartMedia), and the Compact Flash Association (Compact Flash). SMSC does not make such licenses or technical information available; does not promise or represent that any such licenses or technical information will actually be obtainable from or through the various persons or entities (including the media standard companies, forums, and associations), or with respect to the terms under which they may be made available; and is not responsible for the accuracy or sufficiency of, or otherwise with respect to, any such technical information. SMSC's obligations (if any) under the Terms of Sale Agreement, or any other agreement with any customer, or otherwise, with respect to infringement, including without limitation any obligations to defend or settle claims, to reimburse for costs, or to pay damages, shall not apply to any of the devices made the subject of this document or any software programs related to any of such devices, or to any combinations involving any of them, with respect to infringement or claimed infringement of any existing or future patents related to solid state disk or other flash memory technology or applications ("Solid State Disk Patents"). By making any purchase of any of the devices made the subject of this document, the customer represents, warrants, and agrees that it has obtained all necessary licenses under then-existing Solid State Disk Patents for the manufacture, use and sale of solid state disk and other flash memory products and that the customer will timely obtain at no cost or expense to SMSC all necessary licenses under Solid State Disk Patents; that the manufacture and testing by or for SMSC of the units of any of the devices made the subject of this document which may be sold to the customer, and any sale by SMSC of such units to the customer, are valid exercises of the customer's rights and licenses under such Solid State Disk Patents; that SMSC shall have no obligation for royalties or otherwise under any Solid State Disk Patents by reason of any such manufacture, use, or sale of such units; and that SMSC shall have no obligation for any costs or expenses related to the customer's obtaining or having obtained rights or licenses under any Solid State Disk Patents. SMSC MAKES NO WARRANTIES, EXPRESS, IMPLIED, OR STATUTORY, IN REGARD TO INFRINGEMENT OR OTHER VIOLATION OF INTELLECTUAL PROPERTY RIGHTS. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES AGAINST INFRINGEMENT AND THE LIKE. No license is granted by SMSC expressly, by implication, by estoppel or otherwise, under any patent, trademark, copyright, mask work right, trade secret, or other intellectual property right. **To obtain this software program the appropriate SMSC Software License Agreement must be executed and in effect. Forms of these Software License Agreements may be obtained by contacting SMSC.
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Chapter 2
2.1
Acronyms & Definition
Acronyms
SM: SmartMedia SMC: SmartMedia Controller FM: Flash Media FMC: Flash Media Controller ECC: Error Checking and Correcting CRC: Cyclic Redundancy Checking
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Chapter 3
Pin Tables
Table 3.1 - USB97C242 100 Pin Package NAND FLASH/SMARTMEDIA INTERFACE (17 PINS) D1 D2 D5 D6 CLE nRE nB/R nCE USB INTERFACE (7 PINS) USBLOOPFLTR FS+ FSMEMORY/IO INTERFACE (29 PINS) MA1 MA2 MA5 MA6 MA9 MA10 MA13 MA14 MD1 MD2 MD5 MD6 nMWR nMCE nIOR MISC (21 PINS) GPIO1 GPIO20 GPIO5 GPIO6 XTAL2 nRESET nCS5 nCS6 nCS1 nCS2 nTEST1 POWER, GROUNDS, AND NC (26 PINS) TOTAL 100
D0 D4 ALE nWP nWPS USB+ RTERM MA0 MA4 MA8 MA12 MD0 MD4 nMRD nIOW ROMEN GPIO4 XTAL1/CLKIN nCS4 nCS0 nTEST0
D3 D7 nWE nCD
RBIAS
MA3 MA7 MA11 MA15 MD3 MD7
GPIO3 GPIO7 nCS7 nCS3
3.1
100 Pin List
Table 3.2 - 100 Pin TQFP PIN # 1 2 3 4 5 6 7 8 NAME MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA PIN # 8 26 8 27 8 28 8 29 8 30 8 31 8 32 8 33 NAME MD5 MD6 MD7 nMRD nMWR VSSIO nMCE nIOW MA PIN # 8 51 8 52 8 53 8 54 8 55 8 56 8 57 8 58 NAME MA PIN # nWE 12 76 nWP 12 77 nCE 8 78 nWPS 79 nB/R 80 nCD 81 nCS0 82 VDDCORE 83 NAME RBIAS VDDA FS+ USB+ USBFSRTERM VSSA MA
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PIN # 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
NAME MA8 MA9 MA10 VDDCOR E MA11 VSSCOR E VSSIO MA12 MA13 MA14 MA15 VDDIO MD0 MD1 MD2 MD3 MD4
MA PIN # 8 34 8 8 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NAME nIOR ROMEN D0 D1 D2 VDDCOR E D3 VSSCOR E D4 VDDIO D5 D6 D7 ALE VSSIO nRE CLE
MA PIN # NAME 8 59 nCS1 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 VSSCORE nCS2 VDDIO nCS3 nCS4 VSSIO nCS5 nCS6 nCS7 NC NC NC NC NC NC NC
MA PIN # 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
12 12 12
8
NAME XTAL1/CL KIN XTAL2 VSSP LOOPFLT R VDDP GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 nRESET VSSIO nTEST0 VDDIO nTEST1
MA
8 8 8 8 8 8 8
12
8 8 8 8 8 8 8 8 8
12 12 12 12 12 24 12
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Chapter 4
Pin Configuration
75 RBIAS VDDA FS+ USB+ USBFSRTERM VSSA XTAL1/CLKIN XTAL2 VSSP LOOPFLTR VDDP GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 nRESET VSSIO nTEST0 VDDIO nTEST1
NC NC NC NC NC NC NC nCS7 nCS6 nCS5 VSSIO nCS4 nCS3 VDDIO nCS2 VSSCORE nCS1 VDDCORE nCS0 nCD nB/R nWPS nCE nWP nWE 51 CLE nRE VSSIO ALE D7 D6 D5 VDDIO D4 VSSCORE D3 VDDCORE D2 D1 D0 ROMEN nIOR nIOW nMCE VSSIO nMWR nMRD MD7 MD6 MD5 25
USB97C242
1
SMSC USB97C242
MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 VDDCORE MA11 VSSCORE VSSIO MA12 MA13 MA14 MA15 VDDIO MD0 MD1 MD2 MD3 MD4
Figure 4.1 - 100 Pin TQFP
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Chapter 5
A uto address generators
Block Diagram
512 B ytes E P 2 TX/RX B uffer B 512 B ytes E P 2 TX/RX B uffer A 64 B ytes E P 1RX 64 B ytes E P 1T X 64 B ytes E P 0RX E P 0RX_B C A ddress 64 B ytes E P 0T X
1.25KB SRAM
A ddress EP0TX_B C A ddress
Flash M edia C ontroller (FM C )
60M H z
C S [7:0]
M em ory C ards
Data Buss
Address MUX
EP1TX_B C
A ddress
32 B it
E P 1R X_B C R A M W R_A /B
A ddress A ddress
SM/ N A N D Flash NA N D Flash N A N D Flash
Latch phase 0, 2 S IE
Latch phase 3 8051
Latch phase 1 FM C
DA TA
R A M RD _A /B
A ddress Address Register
D ata @ 32 bit 15Mhz
Flash M edia DM A U nit
ECC C ontrol/ S tatus
SM Controller C ontrol/ S tatus
N A N D Flash
N A N D Flash XDATA & SFR Address and Data busses N A N D Flash N A N D Flash
C locked byP hase 0, 2 C lock S IE ( S erial Interface E ngine ) 32 bit 15M Hz Data B uss
N A N D Flash 12K B yte S cratchpad SRAM
S IE C ontrol Regs
U S B 2.0 P HY ( Transciever )
Configuration and C ontrol
G P IO
7 pins
C lock G eneration 7 pins Interrupt Controller O sc
S cratchpad S R A M (768 B yte)
48K B RO M
ROMEN
M E M /IO B us XTAL
29pins
P rogram M em ory/ IO B us
FAS T 8051 CPU CORE
C LO CK O U T
12 M H z
Clocked by P hase 3 Clock
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Chapter 6
Pin Descriptions
This section provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface. The "n" symbol in the signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When "n" is not present before the signal name, the signal is asserted when at the high voltage level. The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of "active low" and "active high" signal. The term assert, or assertion indicates that a signal is active, independent of whether that level is represented by a high or low voltage. The term negate, or negation indicates that a signal is inactive. Table 6.1 - USB97C242 Pin Descriptions BUFFER TYPE
NAME SM Write Protect SM Address Strobe SM Command Strobe SM Data7-0
SYMBOL nWP
DESCRIPTION
NAND FLASH/SMARTMEDIA INTERFACE O12 This pin is an active low write protect signal for the SM or NAND flash device. O12 This pin is an active high Address Latch Enable signal for the SM or NAND flash device. This pin is an active high Command Latch Enable signal for the SM or NAND flash device.
ALE
CLE
O12
D[7:0]
I/OPU12 These pins are the bi-directional data signal D7-D0. The bi-directional input signal should have an internal weak pull-up resister on the input. This pin is an active low read strobe signal for SM or NAND flash device.
SM Read Enable SM Write Enable SM Write Protect Switch SM Busy or Data Ready SM Chip Enable
nRE
O24
nWE
O12
This pin is an active low write strobe signal for SM or NAND flash device.
nWPS
IPU
A write-protect seal is detected, when this pin is low. This pin has an internal weak pull-up resistor.
nB/R
IPU
This pin is connected to the BSY/RDY pin of the SM or NAND flash device. This pin has an internal weak pull-up resistor. This pin is the active low chip enable signal to the SM or NAND flash device. This pin should be used to support a single SM or NAND flash device only.
nCE
OPU8
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NAME SM Card Detection
SYMBOL nCD
BUFFER TYPE IPU
DESCRIPTION This is the card detection signal from SM device to indicate if the device is inserted. This pin has internal weak pull-up resistor. USB INTERFACE These pins connect to the USB bus data signals. This pin provides the ability to supplement the internal filtering of the transceiver with an external network, if required. A precision 9.09K resistor is attached from ground to this pin to set the transceiver's internal bias currents. A precision 1.5K resistor is attached to this pin from a 3.3V supply.
USB Bus Data USB Transceiver Filter USB Transceiver Bias Termination Resistor Full Speed USB Data Memory Data Bus
USBUSB+ LOOPFLTR
I/O-U
RBIAS
RTERM FSFS+ MD[7:0] I/O-U
These pins connect to the USB- and USB+ pins through 31.6 ohm series resistors. MEMORY/IO INTERFACE When ROMEN = 0, these signals are used to transfer data between the internal CPU and the external program memory. When ROMEN = 1, internal weak pull up are activated to prevent these pins from floating. These signals address memory locations within the external memory.
I/OPU8
Memory Address Bus Memory Read Strobe Memory Read Strobe Memory Chip Enable
MA[15:0]
O8
nMWR
O8
Program Memory Write; active low
nMRD
O8
Program Memory Read; active low
nMCE
O8
Program Memory Chip Enable; active low. This signal shall be de-asserted, when all of the following conditions are met: IDLE bit (PCON.0) is 1. INT2 is negated SLEEP bit of CLOCK_SEL is 1. This signal shall be asserted whenever any of the three conditions are no longer met.
I/O Read Strobe I/O Write Strobe
nIOR nIOW.
O8 O8
This is a active low I/O Read strobe signal of Xdata bus. This is a active low I/O Write strobe signal of Xdata bus.
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NAME Crystal Input/Extern al Clock Input Crystal Output
SYMBOL XTAL1/ CLKIN
BUFFER TYPE ICLKx
DESCRIPTION MISC 12Mhz Crystal or external clock input. This pin can be connected to one terminal of the crystal or can be connected to an external 12Mhz clock when a crystal is not used. 12Mhz Crystal This is the other terminal of the crystal, or left open when an external clock source is used to drive XTAL1/CLKIN. It may not be used to drive any external circuitry other than the crystal circuit. When tied low, an external program memory should be connected to the memory/data bus. The USB97C242 uses this external bus for program execution. When this pin is left unconnected or tied high, the USB97C242 uses the internal ROM for program execution. The state of this pin is latched internally on the rising edge of nRESET to determine if internal or external program memory is used. The state latched is stored in ROMEN bit of GPIO_IN1 register.
XTAL2
OCLKx
Internal ROMEN
ROMEN
IPU
General Purpose I/O
GPIO1
I/O8
This pin may be used either as input, edge sensitive interrupt input, or output. See Chapter 11 for usage by program in internal ROM.
General Purpose I/O
GPIO2
I/OPU8
This pin may be used either as input, edge sensitive interrupt input, or output. See Chapter 11 for usage by program in internal ROM.
General Purpose I/O General Purpose I/O NAND flash Chip Select Signal RESET input TEST Input
GPIO3 GPIO[7:4] nCS[7:0]
I/O8 I/O8 OPU8
This pin may be used either as input, edge sensitive interrupt input, or output. See Chapter 11 for usage by program in internal ROM. These pins may be used either as input, edge sensitive interrupt input, or output. See Chapter 11 for usage by program in internal ROM. These pins can be used to chip enable the NAND flash devices, when multiple NAND flash devices are used.
nRESET nTEST[0:1]
IS
VDD VDDIO VDDP VSSP VDDA VSSA GND
This active low signal is used by the system to reset the chip. The active low pulse should be at least 100ns wide. I These signals are used for testing the chip. User should normally leave them unconnected. POWER, GROUNDS, AND NO CONNECTS +2.5V Core power +3.3V I/O power +2.5 Analog power Analog Ground Reference +3.3V Analog power Analog Ground Reference Ground Reference
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Note: nMCE is normally asserted except when the 8051 is in standby mode.
6.1
Buffer Type Descriptions
Table 6.2 - USB97C242 Buffer Type Descriptions BUFFER I IPU IPD IS I/O4 I/OD4 I/O8 I/OD8 I/OPD8 I/OPU8 O4 O8 OPD8 OPU8 I/O12 I/OPU12 OPU12 OPD12 O12 OD12 ICLKx OCLKx I/O-U DESCRIPTION Input Input with internal weak pull-up resistor. Input with internal weak pull-down resistor. Input with Schmitt trigger Input/Output with 4mA drive Input/Open drain output ... 4mA sink Input/Output with 8mA drive Input/Open drain output ... 8mA sink Input/Output with 8mA drive and controlled weak pull down. Input/Output with 8mA drive and controlled weak pull up. Output with 4mA drive Output with 8mA drive Output with 8mA drive and controlled weak pull down. Output with 8mA drive and controlled weak pull up. Output with 12mA drive Input/Output with 12mA drive and controlled weak pull up on input. Output with 12mA drive and controlled weak pull up. Output with 12mA drive and controlled weak pull down. Output with 12mA drive Open drain....12mA sink XTAL clock input XTAL clock output Defined in USB specification
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Chapter 7
7.1
DC Parameters
Maximum Guaranteed Ratings
Operating Temperature Range........................................................................................................................... 0oC to +70oC Storage Temperature Range ............................................................................................................................-55o to +150oC Lead Temperature Range (soldering, 10 seconds) ..................................................................................................... +325oC Positive Voltage on any pin, with respect to Ground ........................................................................................................ 5.5V Negative Voltage on any pin, with respect to Ground......................................................................................................-0.3V Maximum VDD, VDDP ........................................................................................................................................................+3.0V Maximum VDDIO, VDDA ......................................................................................................................................................+4.0V *Stresses above the specified parameters could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. Note: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. When this possibility exists, it is suggested that a clamp circuit be used. Table 7.1 - DC Electrical Characteristics (TA = 0C - 70C, VDDIO, VDDA= +3.3 V 10%, VDD, VDDP = +2.5 V 10%,) PARAMETER I Type Input Buffer Low Input Level High Input Level ICLK Input Buffer Low Input Level High Input Level Input Leakage (All I and IS buffers) Low Input Leakage High Input Leakage VILI VIHI 2.0 0.8 V V TTL Levels SYMBOL MIN TYP MAX UNITS COMMENTS
VILCK VIHCK 2.2
0.4
V V
IIL IIH
-10 -10
+10 +10
uA uA
VIN = 0 VIN = VDDIO
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PARAMETER O8 Type Buffer Low Output Level
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
VOL
0.4
V
IOL = 8 mA @ VDDIO = 3.3V
High Output Level
VOH
2.4
V
IOH = -4mA @ VDDIO = 3.3V
Output Leakage
IOL
-10
+10
uA VIN = 0 to VDDIO (Note 7.1)
I/O8 Type Buffer Low Output Level VOL 0.4 V IOL = 8 mA @ VDDIO = 3.3V
High Output Level
VOH
2.4
V
IOH = -4 mA @ VDDIO = 3.3V
Output Leakage
IOL
-10
+10
A VIN = 0 to VDDIO (Note 7.1)
I/O12 Type Buffer Low Output Level VOL 0.4 V IOL = 12 mA @ VDDIOE = 3.3V
High Output Level
VOH
2.4
V
IOH = -6mA @ VDDIO = 3.3V
Output Leakage I/O24 Type Buffer Low Output Level
IOL
-10
+10
A
VIN = 0 to VDDIO (Note 7.1,Note 7.3)
VOL
0.4
V
IOL = 24 mA @ VDDIO = 3.3V
High Output Level
VOH
2.4
V
IOH = -12 mA @ VDDIO = 3.3V
Output Leakage
IOL
-10
+10
A
VIN = 0 to VDDIO (Note 7.1,Note 7.3)
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PARAMETER IO-U Note 7.2 Supply Current Unconfigured
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
ICCINIT
85 60 85 60 110 70 150 150
mA mA mA mA A
Supply Current Active
ICC
Supply Current Standby
ICSBY
@ VDD, VDDP = 2.5V @ VDDIO, VDDA = 3.3V @ VDD, VDDP = 2.5V @ VDDIO, VDDA = 3.3V @ VDD, VDDP = 2.5V @ VDDIO, VDDA = 3.3V
Note 7.1 Note 7.2 Note 7.3
Output leakage is measured with the current pins in high impedance. See Appendix A for USB DC electrical characteristics. Output leakage is valid only on pins without internal weak pull ups or pull downs.
7.1.1
Capacitance TA = 25C; FC = 1MHz; VDD, VDDP = 2.5V
LIMITS TYP MAX 20 10 20
PARAMETER Clock Input Capacitance Input Capacitance Output Capacitance
SYMBOL CIN CIN COUT
MIN
UNIT TEST CONDITION pF All pins except USB pins (and pins under test tied pF to AC ground) pF
SMSC USB97C242
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Revision 1.4 (02-16-06)
DATASHEET
USB 2.0 Flash Drive Controller Datasheet
Chapter 8
AC Specifications
Refer to the appropriate specification document in the chapter of "Reference" for each flash media device or USB interface.
SMSC USB97C242
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Revision 1.4 (02-16-06)
DATASHEET
USB 2.0 Flash Drive Controller Datasheet
Chapter 9
Package Outline
Figure 9.1 - 100 Pin TQFP Package Outline, 12x12x1.4 Body (Rev A) Table 9.1 - 100 Pin TQFP Package Parameters (Rev A) MIN NOMINAL MAX REMARKS ~ ~ 1.60 Overall Package Height A 0.05 ~ 0.15 Standoff A1 1.35 ~ 1.45 Body Thickness A2 13.80 ~ 14.20 X Span D 11.80 ~ 12.20 X body Size D1 13.80 ~ 14.20 Y Span E 11.80 ~ 12.20 Y body Size E1 0.09 ~ 0.20 Lead Frame Thickness H 0.45 0.60 0.75 Lead Foot Length L ~ 1.00 ~ Lead Length L1 0.40 Basic Lead Pitch e o ~ 7o Lead Foot Angle 0 0.13 0.16 0.23 Lead Width W 0.08 ~ ~ Lead Shoulder Radius R1 0.08 ~ 0.20 Lead Foot Radius R2 ~ ~ 0.08 Coplanarity ccc Notes: 1 Controlling Unit: millimeter. 2 Tolerance on the position of the leads is 0.035 mm maximum. 3 Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. 4 Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. 5 Details of pin 1 identifier are optional but must be located within the zone indicated.
SMSC USB97C242
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Revision 1.4 (02-16-06)
DATASHEET
USB 2.0 Flash Drive Controller Datasheet
Chapter 10 Reference
1. 2. 3. 4. 5. 6. 7. SmartMediaTM Electrical Specification Version 1.30 SmartMediaTM Physical Format Specifications Version 1.30 SmartMediaTM Logical Format Specifications Version 1.20 SMIL (SmartMedia Interface Library) Software Edition Version 1.00, Toshiba Corporation, 01, July, 2000 SMIL (SmartMedia Interface Library) Hardware Edition Version 1.00, Toshiba Corporation, 01, July, 2000 K9K2G08U0M, 256Mx8 Bit NAND Flash Memory Data Sheet, Samsung. Universal Serial Bus Specification Rev 2.0
SMSC USB97C242
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Revision 1.4 (02-16-06)
DATASHEET
USB 2.0 Flash Drive Controller Datasheet
Chapter 11 GPIO Usage Table
Table 11.1 - GPIO Usage NAME GPIO1 H ACTIVE LEVEL SYMBOL Flash Media Activity LED DESCRIPTION AND NOTE Indicates media activity. Media or USB cable must not be removed with LED lit. Active High. Ready/Busy# line from NAND Flash chips 0, or 0 & 4 USB V bus dectect Ready/Busy# line from NAND Flash chips 1, or 1 & 5 In Rom -03; HS_LED output indicator; in later ROM patterns, the Ready/Busy# line from NAND Flash chips 2, or 2 & 6 A16 address line when external Rom is used; unused output otherwise. Ready/Busy# line from NAND Flash chips 3, or 3 & 7
GPIO2 GPIO3 GPIO4 GPIO5
H H H H
Ready/Busy# 1/4 V_BUS Ready/Busy# for Chips 1/5 HS_IND/Ready/Busy# 2/6
GPIO6
H
A16
GPIO7
H
Ready/Busy# 3/7
SMSC USB97C242
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Revision 1.4 (02-16-06)
DATASHEET
USB 2.0 Flash Drive Controller Datasheet
Chapter 12 Typical Application
Contact SMSC Sales for the latest reference designs and information and details about software licenses and the latest capabilities/features included in current production versions of the internal ROM.
SMSC USB97C242
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Revision 1.4 (02-16-06)
DATASHEET

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